1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the invention relates to electrically erasable and programmable flash memory devices.
2. Description of the Related Art
Flash memory devices are one type of nonvolatile memory and more particularly, one type of electrically erasable and programmable read-only memory (EEPROM). In this type of memory, data may be written to a number of memory blocks during a single programming operation, and data may be erased from one memory block during a single erase operation As a result of these capabilities, flash memory is particularly useful in systems requiring rapid and effective read/programming operation, and systems that copy blocks of data from one memory section to another memory section. However, like all forms of EEPROM, flash memory incorporates a memory cell structure having one or more material films insulating a charge storage element. Such insulating films tend to break down with repeated use of the memory cell and may ultimately fail.
Like all nonvolatile memories, flash memory is able to retain stored data without power being constantly supplied. In addition, flash memory exhibits excellent resistance to mechanical shocks, good power consumption characteristics, and fast data access during read operations. With such features, flash memory has been widely incorporated as the data storage component of many contemporary electronic devices, particularly those running off batteries, such as cellular phones, personal digital assistants (PDA), digital cameras, portable gaming consoles, and MP3 players. Further, flash memory devices are widely employed as code storage elements in host devices such as high-definition TVs, digital versatile disks (DVDs), routers, and global positioning systems (GPSs).
Flash memory is generally available in two types: NOR and NAND. These designations are drawn from the logical arrangement of gates within the respective flash memory types. Contemporary flash memory devices may further be categorized as single data bit per memory cell or multi-bit per memory cell devices
Regardless of logical gate type or data bit per memory cell capabilities, all flash memory incorporates a floating gate element storing charge indicative of data state. An important consideration relative to this element is its reliability under operating stress (or operating endurance). That is, the number of programming/erasing cycles that may be performed on a flash memory cell before degradation of its data retention characteristics is an important quality metric.
Stored charge (e.g., electrons) may leak from a floating gate due to a number of mechanisms, including the emission of thermions, charge diffusion, drift due to ionic impurities, stress under programming disturbances, etc. As the charge leakage from a floating gate varies, the operating threshold voltage for the memory cell will change. Similarly, charge migration from an associated control gate to the floating gate results in a change to the threshold voltage. These potential changes to threshold voltage are directly related to the insulating quality of films associated with the floating gate.
Unfortunately, repetitive programming/erasing cycles stress the insulating film(s) (e.g., oxides) associated with the floating gate, and the threshold voltage of unit memory cells may gradually change (e.g., be reduced) over time. As indicated by the broken line in Figure (FIG.) 1, the distribution profile for a programmed memory cell may shift to a lower voltage level. In some instances, memory cells having a shifted distribution profile (see, shaded region of FIG. 1) may actual exhibit a threshold voltage lower than a defined program-verifying voltage Such a circumstance will result in a read fail due to a decrease in read margin relative to the threshold voltage.